Jayaraj is an LFX mentee at RISC-V International, actively engaged in studying the RISC-V Instruction Set Architecture (ISA) and its applications. With a passion in computer archtitecture, deisgn and verification, he contribute to the development and promotion of the RISC-V ecosystem. Through his contribution in Sliderules, provide interactive learning materials and practical examples to enhance understanding of RISC-V architecture. Committed to open-source collaboration and knowledge sharing, his passion lies in sharing knowledge and helping fellow beginners understand the fundamental concepts of RISC-V. By bridging the gap between academia and open-source communities, he strives to create a welcoming environment for newcomers and contribute to the growth of RISC-V in collaboration with the free and open source software communities like Debian.

Cancelled Talks:

RISC-V meets Information Design: the Interactive "Sliderules" Instruction Set Architecture Cheatsheets

The RISC-V ISA specification PDFs are sometimes not so friendly to beginners, and retrieving specific transversal information is at times a bit cumbersome. We introduce a solution: the “Sliderules” Cheatsheets, which is an ultra-beginner friendly source of detailed documentation about the RISC-V ISA. Thanks to a careful 2D layout and alignment of the ISA information, hence the name “Sliderules”, the original RV32IMAC static cheatsheets were designed with the idea of making students “play” an assembler, enabling them to quickly convert assembly to binary and back. Unfortunately, the original RV32IMAC project is not version controlled and particularly human-error-prone, and thus difficult to maintain: thanks to an ongoing LFX/RISC-V Mentorship program, the project is currently in the process of being ported to the web as an interactive application, while also being expanded to RV64GC.